Background: Interconnects in electronic systems are a basic building block that enable electrical signals to move through the different components of the system. The capability of the interconnect to transport signals reliably is a critical factor in high performance electronic systems. Overcoming barriers in the development of interconnect technology can lead to higher performance computing and communication systems with a variety of applications. New ways to fabricate interconnects within integrated chips (IC) and other platforms is a key area of R&D focus, especially for mobile and portable electronic products.
Technology: Muhannah Bakir, Chaoqi Zhang, and Paul Kim Jo in Electrical and Computer Engineering at Georgia Tech have discovered a novel process that enables the fabrication of flexible, concave and convex interconnect structures. The process is fully CMOS (Complementary Metal-Oxide Semiconductor) compatible and can be performed at very high densities that are becoming commonplace in the fabrication of ICs. The invention focuses on developing mechanically, flexible interconnects with variable tip ends and heights without requiring additional lithography steps during the fabrication process. Fabrication of temporary and permanent interconnects are possible using this process. Another innovative aspect of this invention is the capability to form a combination of concave and convex interconnects with different heights, tips and thicknesses. This allows for tailoring the interconnect characteristics to the pitch and range of deformation for a particular IC component. An extension of the process is the ability to form ‘s-shaped’ vertical interconnects with excellent mechanical strength and good contact characteristics. The inventors have successfully demonstrated the ability to fabricate a variety of tip-shaped (other than concave, convex and s-shaped) mechanically, flexible interconnects with controlled thicknesses within a minimum number of process steps.
Potential Commercial Applications: Electronic systems ranging from microelectronics, photonics, bioelectronics and 3D chips would be able to use this invention to achieve improved performance. Interconnects of the type enabled by this invention would find special applicability in small form factor systems, such as smartphones and compact electronic products, where space is at a premium. Other general application areas where this invention would have an immediate impact are packaging, testing, burn-in and wafer-level probing.
Co-fabrication of very complex interconnect structures for developing and testing different system topologies
Improved system performance while increasing packaging density with little or no impact on the fabrication process steps used
Complex shapes easily fabricated without compromising the mechanical strength or the electrical performance
Key interconnect characteristics can be manipulated to fit to the specific component or system